ADAU1860BCBZRL
原装正品ADI
The ADAU1860 is a codec with three inputs and one output that incorporates two digital signal processors (DSPs). The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise canceling earphone. With the addition of just a few passive components, the ADAU1860 provides a complete earphone solution. APPLICATIONS Noise canceling handsets, headsets, and headphones Bluetooth active noise canceling (ANC) handsets, headsets, and headphones Personal navigation devices Digital still and video cameras Musical instrument effect processors Multimedia speaker systems Smartphones
特性
• Programmable FastDSP audio processing engine• Up to 768 kHz sample rate• Biquad filters, limiters, volume controls, mixing • Tensilica HiFi 3z DSP core• Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator• Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz• 336 kB total memory• JTAG debug and trace• Low latency, 24-bit ADCs and DAC• 106 dB SNR (signal through ADC with A-weighted filter)• 110 dB combined SNR (signal through DAC and headphone with A-weighted filter)• Programmable double precision MAC engine for maximum 24-stage equalizer• Serial port sample rates from 8 kHz to 768 kHz• 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions)• 3 differential or single-ended analog inputs, configurable as microphone or line inputs• 8 digital microphone inputs• Analog differential audio output, configurable as either line output or headphone drive• 2 PDM output channels• PLL supporting any input clock rate from 30 kHz to 36 MHz• 4 channel asynchronous sample rate converters (ASRCs)• 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode)• 8 interpolators and 8 decimators with flexible routing• Power supplies• Analog AVDD at 1.8 V typical• Digital I/O IOVDD at 1.1 V to 1.98 V• Digital DVDD at 0.85 V to 1.21 V• Headphone HPVDD at 1.8 V typical• Headphone HPVDD_L at 1.2 V to HPVDD• Control/communication interfaces• I2C, SPI, or UART control ports• Master quad SPI (QSPI)• UART communication port• Self-boot from QSPI flash• Flexible GPIO and IRQ• 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP